SUNY RSFQ Cell Library

XOR

Schematic

Unless otherwise stated, all parameters here and below
are in PSCAN units (for 3.5 um).

Moore diagram

How it works

Operation of the circuit is as follows: an input SFQ pulse "A" ("inA") enters through junction J1 and is stored in the quantizing loop J1-J2-L1-L18-J4-J5, or loop "A". Similarly, an SFQ pulse applied to input "B"("inB") enters through junction J8 and is stored in loop "B": J8-J7-L2-L18-J4-J5. When both loop "A" and loop "B" are empty, the incoming clock pulse "CLOCK" ("clk") induces a 2*Pi phase leap in junction J6 and there is no output. We have, therefore, the 0+0=0 function (here "+" stands for modulo 2 addition operator, or XOR). When there was only input pulse before the clock, the current through the quantizing inductance of one of the loops biases the two-junction comparator J4-J5 so that the next clock pulse flips junction J5 (rather than J6) and we get and SFQ pulse at the output of the XOR. In other words, we have 1+0=0+1=1. The output SFQ voltage pulse across J5 clears the loop which contained the flux quantum and is at the same time applied to the empty loop. This is why the buffer junctions J2 and J7 are necessary. They prevent junctions J1 and J8 from flipping (and thus injecting parasitic backward-moving SFQ pulses into the input circuits) when the output pulse is generated. The slowest and most untrivial operation is 1+1=0. It is performed by junction J4 which flips when both quantizing loops have and SFQ inside. This process starts asynchronously, as soon as both "A" and "B" are in and has to finish before the arrival of the clock signal. Ideally, when the clock pulse arrives, it finds the gate in the same state as in the case of zero inputs. Junctions J3 and J9 are optional, they serve as buffers in case 2 "A"'s or 2 "B"'s arrive before the clock pulse.

The latch was simulated and optimized with inputs and output matched with special JTLs:

Here's are all the files (you can also view them online ) necessary to simulate the circuit with PSCAN. The I/O JTLs used for optimization of this XOR are standard.

Waveforms

The waveforms show voltages across all 9 junctions of the XOR for the input sequence which is better understood if we consider the corresponding SFQHDL logic waveforms:

The test sequence was as follows: there was a total of 7 input clock pulses (/JTLCLK/IN) applied to the gate with 2 "A" pulses between the 1st and 2nd clock (/JTLA/IN), 2 "B" pulses between 2nd and 3rd clocks, 1 "A" between 3rd and 4th clock, 1"B" between 4th and 5th clock, "A" then "B" between 5th and 6th clock pulses and finally, "B" then "A" between 6th and 7th clocks. The exact SFQHDL description of the cell can be found here .

Layout

This version was laid out for fabrication by Hypres, Inc. Layout size is 120x90 um2.

And here's an actual micro-photograph of the design:

References

This XOR gate was first described in the seminal review of Profs. Likharev and Semenov:

O.A. Mukhanov, S.V. Polonsky, and V.K. Semenov, "New Elements of The RSFQ Logic Family", IEEE Trans. on Magn., vol. 27, pp. 2435-2438, March 1991.
K. Likharev and V. Semenov, "RSFQ logic/memory family: A new josephson-junction technology for sub-terahertz clock-frequency digital systems", IEEE Trans. Appl. Supercond., vol. 1, pp. 3-28, March 1991.

Experimental low frequency results were published a few years later:

S. Polonsky, J. Lin, and A. Rylyakov, "RSFQ arithmetic blocks for DSP applications", IEEE Trans. Appl. Supercond., vol. 5, pp. 2823-26, June 1995. (gzipped Postscript file is available here )

A rather detailed study of the bit error rates of low-power XOR gates at speeds of up to 25 GHz was reported in:

A. Rylyakov and K. Likharev "Pulse Jitter and Timing Errors in RSFQ circuits", Report at 1998 Applied Superconductivity Conference (Palm Desert, CA, September 1998. (gzipped Postscript file is available here )

Also, a somewhat outdated writeup can be found in A. Rylyakov's online thesis .

Send comments to:
A. Rylyakov sasha@rsfq1.physics.sunysb.edu

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