D Flip-Flop with Complementary Outputs

Schematics

All parameters are in PSCAN dimensionless units.

This particular flip-flop has been optimized primarily for the lowest possible static I/O currents and matching I/O impedance, and secondary for the highest XI and XJ margins.

Mealey Machine

How It Works

This is just a combination of a D flip-flop J8-L13-L34-J11 and an invertor J27-J28-L29-L39-L31-J20-J40 with common read-out, and it seems to be the most robust implementation of the DFFC. Depending on whether or not there was a data pulse D between two consequitive clock pulses C, the will be a pulse either on output NOUT (QNot on the Mealey diagram) or OUT (Q).

Files, necessary to simulate the circuit.

Transient Waveforms

Transition	Delay	Aplha
C/QNot	14.2	28
C/Q	19.2	25.5

Layout

This particular design has never been fabricated.

References

1. K. Likharev and V. Semenov, "RSFQ Logic/Memory Family: a New Josephson Junction Technology for Sub-Teraherz Clock Frequency Digital Systems", IEEE Trans. on Appl. Supercond., March 1991, vol. 1:(1), pp. 3-28.
2. A. Yu. Kidiyarova-Shevchenko, A. F. Kirichenko, S. V. Polonsky, and P. N. Shevchenko, "New Elements of RSFQ logic/memory family", Ext. Abstr. of 3'd ISEC91, (1991), p.200

Other versions of the DFFC can be found in:

1. S. Polonsky, V. Semenov, P. Bunyk, A. Kirichenko, and others, "New RSFQ circuits," IEEE Trans. on Appl. Supercond., March 1993, vol. 3:(1), pp. 2566-2577.
2. A.F. Kirichenko, V.K. Semenov, Y.K. Kwong, and V. Nandakumar, "4-bit Single Flux Quantum Decoder," IEEE Trans. on Appl. Supercond., vol. 5, no. 2, 1995, p. 2857.
3. Z. Deng, N. Yoshikawa, S. Whiteley, and T. Van Duzer, "Data-Driven Self-Timed RSFQ Digital Integrated Circuit and System", IEEE Trans. on Appl. Supercond., June 1997, vol. 7:(2), pp. 3634-3637.