SUNY RSFQ CELL LIBRARY

SUNY RSFQ Cell Library

Timing-Safe Optimization for Interconnectivity

General Principles

Additional restrictions have to be imposed on a single RSFQ circuit during the optimization so that the margins and the timing parameters of the circuit do not change after it is embedded in a real environment. We call this "timing-safe optimization" or "optimization for interconnectivity".

We want all cell I/O ports behave as if they were segments of a standard Josephson transmission line (JTL).

During the simulation, we replace one of the segments of JTL by the simulated circuit and request that the timing parameters and the margins of the other two segments do not change. This can be achieved by satisfying the following requirements:

zero current flows through the simulated cell boundary (the phase on cell input/output Josephson junctions is the same as on "standard" JTL junctions),
the ratio of the critical currents of the largest output junction and the smallest input junction is no larger than sqrt(2), and
the inductance of the cell ports L_in and L_out (including the inductance of the Josephson junctions!) matches the input/output inductance of the JTL (~1.45 PSCAN units for our "standard" JTL).

In this case, the first and the last segments of the JTL electrically "see" the simulated circuit exactly as if it were yet another segment of a JTL.

Notice that because a cell may have more than one internal state, these conditions can only be satisfied either in a certain state or on average. We optimize our cells to achieve relatively small average current flow through input/output inductances with absolute value of about 0.03 PSCAN units. We believe that in this case the margins of the cell do not deteriorate by more than 1.5%.

Whatever optimization procedure we choose for our circuit, it should be subject to these constraints. Therefore, finally the circuit is optimized to work in the surrounding of other circuits with "standard" input and output impedances and zero cross-boundary currents. When the optimization is completed and required margins are achieved, the circuit can be used in an arbitrary environment, provided that the neighbors satisfy the same boundary conditions .

Example A (by D. Zinoviev)

To demonstrate this statement, the following experiment was done. We have optimized a set of frequently used RSFQ cells (D flip-flop with complementary outputs, T flip-flop, D² flip-flop, Josephson transmission line, and pulse splitter) using the "standard" optimization environment and imposing the "standard" restrictions.

The "standard" environment is shown in the Figure below. It consists of 1.5 segments of a JTL. The circuit under test input and output interfaces that when merged JSOUT/L5/IIN constitute a complete segment of the JTL. We request that the dc current through L5 is on average approximately equal to IIN. Thus, we ensure that a) no current flows through pin STD, and b) inductances as seen by IIN and its mirrored counterpart within the tested circuit, are equal.

For every optimized cell, we measured all parameter margins and delays for every transition in the corresponding Mealy machine as functions of all global parameters XI, XJ, XL, and XR. Then, we constructed the 1-bit address interpreter mentioned above by putting necessary elementary cells together. No additional optimization has been done. The simulation results show that:

The parameter margins of the interpreter remain virtually the same, and
The transition and transport delays in the cells embedded in the interpreter do not differ significantly from the corresponding delays in the cells in the "standard" environment (Figure 2). In all cases but one, the difference does not exceed 2 PSCAN units (~1/3 SFQ pulse width). This difference can be easily explained by the fact the delays were estimated manually using analog waveforms like those shown in the Figure.

Example B (by P. Bunyk)

Another set of SUNY library cells was optimized under similar conditions using a manual procedure of achieving zero interface currents. In this case we do not inject current IIN in cell's I/O ports and interconnect cells by a simple inductance (of the value close to that in "standard" JTL).

This set includes:

Layout of all the cells in this set have interface junctions in cell corners so that they are easily accessible from two directions. The interface inductances are only partially included in the cell layout and we write down the value of missing part. When we want to connect two ports of different cells we take the sum of their missing inductances and use an automated tool to draw an inductance of this value along a user-specified path between ports. Since there is no constrains on power line inductance we make power connections separately after all signals are routed. We only have to pay attention to intersect a power line with the signal lines at the right angle to magnetically decouple the current flowing in power line (which can be large!) from the signal lines.

To the right is an example of such a layout (microphotograph of an inverter cell). Data input connection is in the lower-left corner, data output is in the lower-right corner, clock input is in the upper-right corner.

This layout approach (and this set of cells) was used to make an experimental demonstration of a 64-bit integer adder critical path. Though we never simulated the cell combinations that we used in this demonstration, our circuit when fabricated worked with about +-26% power supply current margins.

Maintainer: Dmitry ZINOVIEV